This invention concerns a character display device, in particular a device for display of characters on high-resolution CRT devices.
Existing character display devices use either the character or bit-map method.
FIG. 1 is a block diagram illustrating the configuration of a character-based character display unit. In this figure, a central processing unit (abbreviated as CPU) 1 provides overall system control. A refresh memory (abbreviated as RM) 2 stores character codes, A CRT controller (abbreviated as CRTC) 3 controls CRT display 6 for displaying characters. A character generator (abbreviated as CG) 4 receives character codes and produces pixel signals representing character patterns corresponding to the input character codes. The character generator 4 produces the pixel signals, a set of predetermined number of parallel bits at a time. A parallelserial conversion circuit (abbreviated as PS) 5 converts the parallel bits from the character generator 4 into serial bits. An oscillator circuit 7 (abbreviated as OSC) drives CRT controller 3 and parallel-serial conversion circuit 5.
The following describes the operation of a conventional system, shown in FIG. 1.
The character code written into refresh memory 2 by CPU 1 is read out by CRT controller 3 and sent to character generator 4. Character generator 4 outputs parallel bits representing a character pattern based on this character code. Parallel-serial conversion circuit 5 converts these parallel bits into serial bits. The serial bits are fed to CRT 6 bit by bit, in synchronism with an oscillator circuit 7. Then, CRT 6 displays the resulting data on the display screen. To alter the displayed characters, CPU 1 accesses refresh memory 2 and rewrites the character codes.
FIG. 2 is a block diagram illustrating the configuration of a bit-map character display device. The reference numbers used in FIG. 2 which are identical to those used in FIG. 1 represent the same configuration elements as in FIG. 1. A configuration element in FIG. 2 not present in FIG. 1 is a frame memory (abbreviated as FRM) 8 which has a capacity corresponding to all of the pixels in the display screen of CRT 6 and is used to store the character patterns generated by character generator 4.
The following describes the operation of the conventional system, shown in FIG. 2.
First, CPU 1 accesses character generator 4 and writes one line of character patterns into frame memory 8. Then, CPU 1 accesses character generator 4 again, and writes one line of character patterns for the next line into frame memory 8. By repeating this process as many times as there are lines in a character, the CPU 1 transfers all the character patterns for one character to frame memory 8. CRT controller 3 supplies screen display addresses to frame memory 8. A display signal read from frame memory 8 is converted into serial-bit output by parallel-serial conversion circuit 5 and is sequentially output by oscillator circuit 7 to CRT 6. CRT 6 displays the data thus obtained on the CRT screen.
The character display units of the above configurations are not well suited for use with high-resolution CRTs for the following reasons: In the system using the character method shown in FIGS. 1, refresh memory 2, character generator 4, and parallel-serial conversion circuit 5 must complete their operations within the time it takes for CRT 6 to display a character in a line. Let t be the display time per dot in seconds, and let n be the number of horizontal dots per character; then the display time per character will be tn seconds. Therefore, the extremely small amount of time which the high-resolution CRT allows for the display of a dot has made it difficult to ensure that refresh memory 2, character generator 4, and parallel-serial conversion circuit 5 will complete their operations within the allotted display time per character on that CRT.
As an example, imagine an interlace display mode CRT displaying 2000.times.2000 dots at 50 Hz. On such a CRT, the cycle time (t) per dot will be: EQU t=1/(2000.times.2000.times.50/2)=10 nsec.
On such a CRT, display characters include 24.times.24 dots each, and including the space between characters will involve 28 dots per character, which translates into a display time of tn=10.times.28=280 nsec, since n=28.
It is difficult, however, to ensure completion of operations of refresh memory 2, character generator 4, and parallel-serial conversion circuit 5 within that frame of time.
Systems using the bit-map method shown in FIG. 2, in which CPU 1 rewrites characters by transferring the associated character patterns from character generator 4 to frame memory 8, entail a high CPU 1 overhead, and are slower in performing character refreshing than the character method in FIG. 1.
As an example, assume a system with a 16-bit data bus width and with a character configuration of 24.times.24 dots. To rewrite a character, CPU 1 reads the left 16 bits of the first line of the first character from character generator 4, writing the data into frame memory 8. Then the CPU writes the right 16 bits of the first line into frame memory 8 by a similar process. A character is displayed on the screen by repeating this process through line 24. Thus, to rewrite a character CPU 1 must access character generator 4 48 times and frame memory 8 48 times, for a total of 96 accesses.
By contrast, in the character method of FIG. 1 each character code is stored in refresh memory 2 in 16 bits; given that the data bus width is 16 bits, CPU 1 needs to access refresh memory 2 only once to rewrite a character.